32Mb high-speed low-power asynchronous SRAM
Posted May 27, 2020 • 2 min read
The 32Mb high-speed low-power asynchronous SRAM produced by ISSI, this innovative design strengthens ISSI's long-term commitment to SRAM with the highest quality and performance. 32Mb SRAM provides 12ns access time in the automotive A3 temperature range(-40 ° C to + 125 ° C).
ISSI IS61/64WV204816ALL/BLL is a high-speed 32M-bit static RAM, organized as 2048K words by 16 bits. It is manufactured using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit design techniques can produce high-performance and low-power devices.
When CS # is high(deselected), the device will enter standby mode, in which mode, the power consumption can be reduced by the CMOS input level. The memory can be easily expanded using chip enable and output enable inputs. Activated LOW Write Enable(WE #) controls memory writing and reading. The data byte allows access to the high byte(UB #) and low byte(LB #).
The device is packaged in JEDEC standard 48-pin TSOP(TYPE I) and 48-pin mini BGA(6mm x 8mm), and is used in automotive/industrial/medical/telecom/networking.
SRAM memory is one of random access memory. Each byte or word has an address that can be accessed randomly. SRAM supports three different modes. Each function is described in the "Truth Table" below.
When deselected, the device enters standby mode(CS # high). The input and output pins(I/O0-15) are in a high impedance state. The CMOS input in this mode will save power to the greatest extent.
A write operation problem occurs when the chip(CS #) is selected and the write enable(WE #) input is LOW. The input and output pins(I/O0-15) are in data input mode. Even if OE # is LOW, the output buffer will be closed during this period. UB # and LB # enable the byte write function. By setting LB # low, data from the I/O pins(I/O0 to I/O7) is written to the location specified on the address pins. When UB # is low, the data from the I/O pins(I/O8 to I/O15) is written to this location.
When the chip is selected(CS # is low) and the write enable(WE #) input is high, there is a problem with the read operation. When OE # is LOW, the output buffer is opened for data output. No input is allowed to the I/O pin in read mode. UB # and LB # enable the byte reading function. By enabling LB # LOW, data from memory appears on I/O0-7. And when UB # is low, the data from the memory appears on I/O8-15.
In read mode, the output buffer can be turned off by pulling OE # high. In this mode, the internal device operates as READ, but the I/O is in a high impedance state. Since the device is in read mode, active current is used.
The device includes an on-chip voltage sensor used to initiate the power-on initialization process.
When VDD reaches a stable level, the device requires a tPU(power-up time) of 150us to complete its self-initialization process.
After the initialization is complete, the device can operate normally.